The present invention relates to a multi-processor system, and more particularly to a multi-processor system which may be upgraded from a single-processor system merely by the insertion of an additional processor.
With the rapid pace of development in central processing unit (CPU) technology, obsolescence is a problem to both the manufacturers and the users of personal computers. A product which employs state of the art technology at the time its initial marketing may become obsolete within only a year or less. Personal computers employing 80286 CPUs are current examples. These obsolete computer systems remain operable, but often lack the capability of running software designed for use with systems having more advanced CPUs. In order to run such software on their existing hardware, users are forced to upgrade their systems, and in the process are faced with the following questions: Given a particular system's application, what level of upgrade is required to keep abreast of the current developments in processor and software technology (e.g., would an 80386 provide sufficient computing power, or is an upgrade to a more powerful processor, an 80486 or p5 for example, necessary)? What is the most economical way to expand a computer system from a single-processor system to a multiprocessor computer system in the event that the computing power of a single processor system is insufficient?
There are existing alternatives to the impractical solution of buying a new computer each time a new CPU is developed. One solution involves replacing the circuit board (i.e., mother board or an extended printed circuit board) upon which the system CPU is located with another circuit board having a more sophisticated CPU. Unfortunately, this alternative is not only expensive, it may also be inconvenient in that the user often must contact the original retailer or manufacturer to effect the replacement. A second solution involves providing a specially designed CPU circuit board in the original system on which a prepared location (e.g., an IC socket) is provided for inserting a second CPU when the original CPU on the board requires an upgrade. Upon insertion of the new CPU into the prepared location, the original CPU is disabled. Such a specially designed circuit board is described in copending U.S. patent application Ser. No. 07/872,611 for Upgradeable/Downgradeable Central Processing Unit Chip Computer System, filed on Apr. 22, 1992, and copending U.S. patent application Ser. No. 07/998,879 for Single Chip Replacement Upgradeable/Downgradeable Data Processing System, filed on Dec. 28, 1992, the entire specifications of which are herein incorporated by reference. The second solution provides advantages not enjoyed by the first in that it eliminates the need to replace the whole circuit board. However, several drawbacks still remain. For example, to disable the original CPU is a waste of system resources. Additionally, the problem of converting a single-processor system to a multi-processor system is not addressed.
The problem of converting a single-processor system to a multi-processor system is best understood in the context of the differences between current single-processor and multi-processor systems. FIG. 1 is a simplified block diagram of a single-processor system according to the prior art. The system 10 comprises a CPU 11, a CPU bus 12, a local bus 13, an industry standard expansion bus 14 (shown as an EISA bus, but replaceable by an ISA or a VESA bus), an internal peripheral bus 15 (shown as an XD bus), a CPU-local bus interface 16, a local-EISA bus interface 17, an EISA-XD bus interface 18, a system controller 19 communicating with CPU bus 12 and local bus 13, and a bus controller 20 communicating with local bus 13, EISA bus 14 and XD bus 15. Bus controller 20 includes a coprocessor interface 21 communicating with CPU 11 via a coprocessor error signal line 24 (FERR*), and an error ignore signal line 25 (IGNNE*). When a coprocessor error occurs in CPU 11, coprocessor interface 21 sends an interrupt request signal to an interrupt input terminal (IRQ13) of an interrupt controller 22. Interrupt controller 22 also receives a plurality of interrupt request signals (IRQ1, IRQ3, . . . , IRQ12, IRQ14 and IRQ15) from EISA bus 14, which may be interrupt requests from a printer, a hard disk drive, etc. (not shown). Interrupt controller 22 includes an arbitrator (not shown) for determining the priorities of these interrupt requests. After arbitration, interrupt controller 22 sends an interrupt command to CPU 11 via a signal line 26 (INT), in response to which CPU 11 performs an interrupt routine corresponding to the particular interrupt request.
FIG. 2 is a simplified block diagram of a multi-processor system according to the prior art. The system comprises two CPUs 31 and 41, having associated CPU buses 32 and 42 respectively. CPU buses 32 and 42 communicate with a multi-processor bus 34 via multi-processor bus interfaces 33 and 43 respectively. As in the case of the single-processor system, the multi-processor system comprises a system controller 50, an interrupt controller 51, an EISA bus 38, and XD bus 39, a multiprocessor-EISA bus interface 48 and an EISA-XD bus interface 49. CPUs 31 and 41 have control ports 35 and 45, and coprocessor interfaces 36 and 46 respectively. CPU 41 is provided with an associated interrupt vector port 47. Coprocessor interfaces 36 and 46, perform substantially the same and communicate with CPUs 31 and 41 in substantially the same manner as described above with regard to the single-processor system.
In a multi-processor system, only one CPU can be directly associated with the peripheral input/output (I/O) of the system at any one time. Therefore the interrupt protocol for each CPU is different. When, for example, CPU 31 in the two-processor system of FIG. 2 intends to interrupt CPU 41, CPU 31 writes to a control port 45 of CPU 41. In the system of FIG. 2, other than the interrupt signal caused by a coprocessor error, CPU 31 is the only source of an interrupt signal to CPU 41. Therefore, in response to such an interrupt, CPU 41 acquires necessary information from the interrupt vector port 47 and performs an interrupt routine corresponding to the data written to control port 45.
In contrast, CPU 41 is not the only source of an interrupt signal to CPU 31. There/ore, when CPU 41 intends to interrupt CPU 31, and CPU 41 writes to a control port 35 of CPU 31, the interrupt request must first be arbitrated by interrupt controller 51. As shown in FIG. 2, the interrupt request signal line from CPU 41 to CPU 31 is designated IRQ13. After arbitration, interrupt controller 51 sends an interrupt command to CPU 31, in response to which CPU 31 performs an interrupt routine corresponding to the command of the interrupt controller 51 and the data written to control port 35.
It will be understood from the above discussion that converting a single-processor system to multi-processor system according to the prior art is a complex procedure. As a means of performing this conversion, previous technology has provided two CPU interface card holder slots on the mother board of a computer system (not shown). The CPUs are then combined with circuitry resembling CPU circuit boards 30 and 40 in FIG. 2. When only one CPU circuit board is inserted in the primary of the two holder slots, the system resembles a single-processor system. When it becomes necessary to convert the system from a single-processor system to a multi-processor system, the user purchases another CPU circuit board and inserts it into the secondary holder slot. Unfortunately, this solution may still require the user to contact the original retailer or manufacturer to obtain the second CPU board. Additionally, the user must purchase an entire CPU circuit board which is compatible with the original CPU circuit board. If the original CPU is sufficiently outdated, it may be difficult obtain a compatible CPU circuit board. Finally, in addition to these disadvantages, this solution does not address the problem of CPU upgrade capability.